Developing a high speed memory interface

Type :

Term papers

Pages :

4 pages

Format :

.pdf

Published date :

06/09/2009

Category :

Science & technology

Sub category :

Electronics

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Summary :

Introduction
Memory applications
DDR and DDR2 SDRAM controller
QDR SRAM memory controller
Dedicated double data rate I/O logic elements
LatticeSC switchable I/O termination
RLDRAM1 and 2 memory controller
Embedded memory controller advantages
Conclusion
References

Abstract

A common problem for today's system designers is to reliably interface with their next generation high-speed memory devices. As system bandwidths continue to increase, memory technologies have been optimized for higher speeds and performance. As a result, these next generation memory interfaces are also increasingly challenging to design too. Implementing high-speed, high-efficiency memory interfaces in programmable logic devices such as FPGAs has always been a major challenge for designers. Lattice Semiconductor offers customers a high performance FPGA platform in the Lattice SC to design high-speed memory interface solutions. The LatticeSC family implements various features on-chip that facilitate designing high-speed memory controllers to interface to the next generation high-speed, high performance DDR SDRAM, QDR SRAM, and emerging RLDRAM memory devices.