Developing a high speed memory interface

A common problem for today’s system designers is to reliably interface with their next generation high-speed memory devices. As system bandwidths continue to increase, memory technologies have been optimized for higher speeds and performance. As a result, these next generation memory interfaces are also increasingly challenging to design too. Implementing high-speed, high-efficiency memory interfaces in programmable logic devices such as FPGAs has always been a major challenge for designers. Lattice Semiconductor offers customers a high performance FPGA platform in the Lattice SC to design high-speed memory interface solutions. The LatticeSC family implements various features on-chip that facilitate designing high-speed memory controllers to interface to the next generation high-speed, high performance DDR SDRAM, QDR SRAM, and emerging RLDRAM memory devices.

[...] The controllers are full-featured, fully tested controllers, providing users a low-risk timeto-market solution for high-speed memory interfaces DDR and DDR2 SDRAM Controller Implementing high performance DDR memory interfaces requires careful design of the read and write interface blocks of the memory controller. DDR2 memory devices pose a bigger challenge due to their higher speeds and the bi-directional DQS signal. The LatticeSCM memory controller utilizes onchip PLLs and DLLs, along with programmable delay elements at the input buffers to align the DQS and DQ signals. [...]

[...] Computing and consumer applications require memory solutions like DRAM modules, Flash cards and others that are highly cost sensitive while delivering the performance targets for these applications. This white paper will focus primarily on memory applications in networking and communications. Memory can be on-chip or off-chip. Next generation FPGAs like the LatticeSC have several Megabits (up to 7.8 of RAM onchip. These are useful for simple FIFO structures for nominal buffering requirements. Cost is the primary factor defining the amount of memory on-chip. [...]

[...] The DQS signal from the DDR2 memory is generated from the K_clock sent from the LatticeSC device and then sent back to the FPGA during a read. In order to match the input buffer delay on the DQS/DQS# pins, the K_clock is looped back within the same I/O pad to the input clock routing in order to emulate the delay. The reference to the delay cells are fed by a control bus from the DLL, which is the same control that is used to provide a 90-degree lag on the DQS pins. [...]