Modified locally delayed latching approach for data synchronization in GALS SOCs
Summary :
Table of Contents
- Abstract
- Introduction
- Various schemes for clock generation
- Pausible clock generation
- Data driven clock generation
- Stoppable clock generation
- Locally delayed latching
- Decoupled input port
- Decoupled output port
- Experimental reults
- Conclusions
- References
Abstract
IP core based Systems on chip (soc) require multiple frequency domain clocks and it become difficult to obtain all cores in soc's of the same frequency. As IP core based soc's offer multiple advantages such as high degree of modularity, less time to market, effective integration of complex systems and power saving, gals [1] is the best option for the core based system. The ability to run at different frequencies and different supply voltages contribute to power saving. Each IP core can be independently clocked at different frequencies. When the clock frequencies of various cores are uncorrelated with each other then the data synchronization [2] across the different clock domains is required.
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