Non inclusion property in chip multiprocessors with multi-level cache

Type :

Term papers

Pages :

5 pages

Format :

.pdf

Published date :

06/11/2009

Category :

Science & technology

Sub category :

Electronics

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Summary :

Abstract
Introduction
Related work
Proposed architecture
Coherence protocol
1. Invalidate message
2. Read miss
3. Write miss
4. Write back
Proposed implementation
Conclusion
References

Abstract

Difference between speed of processor and memory is increasing with the advent of new technology. chip multi Processors (CMP) has further increased the pressure on the memory hierarchy. So it has become important to manage on chip memory very judiciously to reduce average memory access time. inclusion property is almost always implemented in present cache hierarchies. One implication of inclusion is that higher level cache1 is always a subset of lower level cache. This replication of data in cache hierarchy reduces the effective cache space available. This paper proposes a non inclusive cache implementation where any data item can be present only at one level in cache hierarchy. So, aggregate cache space available will be more and more data can be present on chip, hence reducing of chip communication. In CMPs multiple cores may need to share same block of data, in this case block may be replicated between cache hierarchies of multiple cores but a block is never replicated in cache hierarchy of a single core. Advantage of implementing inclusion property is ease of maintaining coherence, since coherence has to be maintained only at the last level cache. This paper proposes a coherence protocol which is slight modification of existing protocols, to maintain coherence in non inclusive caches. Keywords: cache memory, inclusion property, chip Multiprocessing, multi-level cache hierarchy, cache Coherence